The subject matter disclosed herein relates to determining placement locations of intra-die wirebond pads in an integrated circuit (IC). More specifically, the subject matter disclosed herein relates to determining placement locations of intra-die wirebond pads in an IC in order to reduce IR (voltage) drop within the IC.
Conventionally, packaging of ICs involves using one of two distinct basic IC packaging approaches, wirebond and C4 flip chip. Generally speaking, wirebond packages are less expensive than C4 flip chip packages. This is primarily because C4 packages are directly attached to the laminate using a fine pitch C4 interconnect. In contrast, wirebond packaging uses the wirebond itself to route from a finer-pad pitch of the chip to a looser-bond pitch of the laminate.
In the case of the C4 flip chip design, the voltage, ground and signal off-chip interconnections can be placed throughout the chip in close proximity to active devices, due to the area-array interconnect technology used by C4 flip chips. As such, the IR drop to an active device in a C4 flip chip design is typically not a major concern.
In contrast, wirebond chips use peripheral interconnect configurations where all the wirebond pads are located on the perimeter of the chip. In the wirebond scenario, IR drop to active devices is generally a concern due to the longer intra-die distance between the wirebond pad and the active devices. This concern may be especially high with respect to the center of the chip.
As silicon technology shrinks in size, the chip operating voltage decreases, and the overall chip current usage increases. Coupled with the growth in die size to accommodate increased functionality, the voltage decrease/current increase may make controlling IR drop difficult.